Chip synchronization performance affected by non-ideal interpolation of bandlimited direct-sequence spread-spectrum signals

Deals with the chip synchronization performance of a fully digitally implemented receiver, operating on a direct-sequence spread-spectrum signal with bandlimited (instead of rectangular) chip pulses. The considered digital receiver operates on samples of the received noisy signal, taken by a fixed clock which is not synchronized to the transmitter clock. The synchronized samples needed for the chip synchronization algorithm are computed by interpolating between the available non-synchronized samples. Because of finite memory, interpolation is non-ideal; hence, some amount of distortion is introduced, which affects the performance of the chip synchronizer. By means of theoretical analysis, the authors investigate the tracking performance of a specific non-coherent early-late chip synchronizer, assuming interpolation of orders zero one and two. They show that non-ideal interpolation can give rise to a loop noise spectrum containing spectral lines, that mainly occur near f=0 when the sampling frequency is very close to an integer multiple of the chip rate. Unless a sufficiently small loop bandwidth is chosen, the contribution of these spectral lines could dominate the tracking error variance, which then becomes much larger than for synchronized sampling