Behavioral fault modeling in a VHDL synthesis environment

This paper proposes new fault models for VHDL behavioral descriptions of combinational logic circuits. The models are developed via abstraction of industry standard single-stuck-line (SSL) faults into the behavioral domain. A functional analysis technique is used to evaluate the effects of SSL faults on gate level implementations. Generalized functional faults are then abstracted into the behavioral domain by examining their relationship with the higher level language construct. Test vectors derived from the new behavioral fault models are applied to synthesized gate level realizations of an example arithmetic logic unit. Resulting gate level fault coverage is determined and used as a measure of effectiveness for the new fault models. Because the behavioral faults are derived from a functional analysis of low level faults, they provide improved fault coverage over previous fault models