Computer modelling: the performance of ATM switch fabric architectures

Investigates the performance of various architectures proposed for ATM switch fabrics, using computer simulation techniques. As the overall objective of the study is to further understand how various configurations of switching elements, queue positions and queue lengths affect the performance of the switch fabric, a general-purpose simulator is required that is able to model the many possible architectural variants of an ATM switch. The performance parameters of particular importance to switch fabric designers are: cell throughput; cell-loss probability; cell-delay; variation of cell delay; and tolerance to faults and overload. It must be possible to study the various switch configurations under different traffic loads, and with different traffic types broadly divided into variable bit rate and constant bit rate