• DocumentCode
    2828520
  • Title

    Enhanced BIST-based diagnosis of FPGAs via boundary scan access

  • Author

    Hamilton, Carter ; Gibson, Gretchen ; Wijesuriya, Sajitha ; Stroud, Charles

  • Author_Institution
    Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA
  • fYear
    1999
  • fDate
    1999
  • Firstpage
    413
  • Lastpage
    418
  • Abstract
    Four methods for accessing BIST for FPGAs via the IEEE 1149.1 standard boundary scan interface are presented and discussed in terms of advantages/disadvantages including their impact on test time and diagnostic resolution. These methods can be used in a variety of FPGA architectures for system level testing and diagnosis
  • Keywords
    boundary scan testing; built-in self test; fault diagnosis; field programmable gate arrays; integrated circuit testing; logic testing; FPGA architectures; FPGA testing; IEEE 1149.1 standard boundary scan interface; boundary scan access; diagnostic resolution; enhanced BIST-based diagnosis; system level diagnosis; system level testing; test time; Built-in self-test; Fault diagnosis; Feedback; Field programmable gate arrays; Flip-flops; Logic arrays; Logic testing; Read-write memory; Routing; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 1999. Proceedings. 17th IEEE
  • Conference_Location
    Dana Point, CA
  • ISSN
    1093-0167
  • Print_ISBN
    0-7695-0146-X
  • Type

    conf

  • DOI
    10.1109/VTEST.1999.766697
  • Filename
    766697
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2828520