DocumentCode :
2828536
Title :
Analyzing the need for ATPG targeting GOS defects
Author :
Isern, E. ; Roca, M. ; Segura, J.
Author_Institution :
Dept. de Fisica, Univ. de les Illes Balears, Palma de Mallorca, Spain
fYear :
1999
fDate :
1999
Firstpage :
420
Lastpage :
425
Abstract :
In this work the need for specific ATPG targeting Gate Oxide Short (GOS) defects is highlighted. Many works have been done to develop ATPG for resistive shorts considering both external bridges between gates, and intra-gate shorts. We show with some examples that in some cases the detection of all detectable intra-gate bridging faults does not imply covering all detectable GOS defects in the circuit. A commercially available standard gate library is analyzed to demonstrate that this problem may appear in real applications. An ATPG tool oriented to detect GOS defects with IDDQ testing is presented. ATPG experiments on a set of benchmark circuits show the efficiency of the proposed tool
Keywords :
VLSI; automatic test pattern generation; fault location; integrated circuit testing; ATPG tool; GOS defects; IDDQ testing; gate oxide short defects; standard gate library; Automatic test pattern generation; Benchmark testing; Bridge circuits; CMOS technology; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Libraries; Semiconductor device modeling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 1999. Proceedings. 17th IEEE
Conference_Location :
Dana Point, CA
ISSN :
1093-0167
Print_ISBN :
0-7695-0146-X
Type :
conf
DOI :
10.1109/VTEST.1999.766698
Filename :
766698
Link To Document :
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