DocumentCode :
2828555
Title :
On the evaluation of arbitrary defect coverage of test sets
Author :
Jain, Abhishek ; Boppana, V. ; Hsiao, Michael S. ; Fujita, M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
fYear :
1999
fDate :
1999
Firstpage :
426
Lastpage :
432
Abstract :
Efficient methods to evaluate the quality of a test set in terms of its coverage of arbitrary defects in a circuit are presented. Our techniques rapidly estimate arbitrary defect coverage because they are independent of specific, physical, fault models. We overcome the potentially explosive computational requirements associated with considering all possible defects by implicitly evaluating multiple faults (of all types) simultaneously and by exploiting the local nature of defects. Our experiments show that a strong correlation exists between stuck-at fault coverage and defects whose behavior is independent of the input vectors. Our techniques are capable of identifying regions in the circuit where defects may escape the test set. We also demonstrate how the chances of detection of an arbitrary defect by a test set vary when a single stuck-at-fault within the vicinity of that defect is detected multiple times by the test set
Keywords :
VLSI; circuit analysis computing; digital integrated circuits; integrated circuit testing; integrated logic circuits; logic testing; arbitrary defect coverage; defect coverage evaluation; multiple faults; stuck-at fault coverage; test set quality; Circuit faults; Circuit testing; Computational modeling; Electrical fault detection; Explosives; Failure analysis; Fault detection; Manufacturing processes; Pattern analysis; Process design;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 1999. Proceedings. 17th IEEE
Conference_Location :
Dana Point, CA
ISSN :
1093-0167
Print_ISBN :
0-7695-0146-X
Type :
conf
DOI :
10.1109/VTEST.1999.766699
Filename :
766699
Link To Document :
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