DocumentCode
2828667
Title
From design-for-test to design-for-debug-and-test: analysis of requirements and limitations for 1149.1
Author
Alves, Gustavo R. ; Ferreira, J. M Martins
Author_Institution
ISEP/DEE, Porto, Portugal
fYear
1999
fDate
1999
Firstpage
473
Lastpage
480
Abstract
The increasing complexity of VLSI circuits and the reduced accessibility of modern packaging and mounting technologies restrict the usefulness of conventional in-circuit debugging tools, such as in-circuit emulators for microprocessors and microcontrollers. However, this same trend enables the development of more complex products, which in turn require more powerful debugging tools. These conflicting demands could be met if the standard scan test infrastructures now common in most complex components were able to match the debugging requirements of design verification and prototype validation. This paper analyses the main debug requirements in the design of microprocessor-based applications and the feasibility of their implementation using the mandatory, optional and additional operating modes of the standard IEEE 1149.1 test infrastructure
Keywords
IEEE standards; VLSI; boundary scan testing; computer debugging; design for testability; integrated circuit design; integrated circuit testing; microprocessor chips; VLSI; design verification; design-for-debug-and-test; microprocessor-based applications; mounting technologies; packaging; prototype validation; standard IEEE 1149.1 test infrastructure; standard scan test infrastructures; Binary search trees; Debugging; Design for testability; Ice; Microprocessors; Packaging; Prototypes; Registers; Testing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1999. Proceedings. 17th IEEE
Conference_Location
Dana Point, CA
ISSN
1093-0167
Print_ISBN
0-7695-0146-X
Type
conf
DOI
10.1109/VTEST.1999.766706
Filename
766706
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