Reconfigurable hardware for real time image processing

Nowadays, a new technology can provide both advantages of ASIC: speed and of parallel processors: flexibility, with limited inconvenience. It is based on dynamically configurable FPGA. These devices can be totally or partially configured in less than 1 ms and their processing speed is approximately 1/3 of the ASIC speed. We present the ARDOISE reconfigurable architecture. The successive algorithms which must be applied sequentially to an input image in real time are swapped on the same FPGA hardware inside the frame duration. The choice of the algorithms can be made in real time and data dependent. In the second section, we discuss the limits on the usefulness of dynamical reconfiguration and give an estimation of the performances in term of silicon reduction. The third section presents an application for real time image segmentation programmed on ARDOISE. In this example, we show that 4 algorithms which use 7 configurations can be applied in real time on images of 512×512 pixels every 40 ms