Design and modeling of a 12-bit SAR ADC IP with non-lumped capacitor array

The design and modeling of a high performance SAR ADC with non-lumped capacitor array is presented in the paper. Based on this mode, the operation method that diminishes nonlinearity parasitical capacitor in the interior DAC is developed to design a 12-bit SAR ADC. An innovative C-carry architecture aimed at the traditional lumped capacitors is discussed. The new capacitor array is composed of identical unit size capacitors, and no capacitors are lumped together. And a high performance CMOS comparator with cross-coupled loads, resetting and clapping method is proposed. The optimal design methods are validated by the simulation result with HSPICE and realized a SAR ADC IP Core which can apply to industrial controllers. The IP core used 0.18um CMOS 1P6M technology, The simulation results show that this design can achieve 12-bit resolution.