Title :
Image and video processing using MAJC 5200
Author :
Sudharsanan, Subramania ; Sriram, Parthasarathy ; Frederickson, Hans ; Gulati, Amit
Author_Institution :
Sun Microsyst. Inc., Palo Alto, CA, USA
Abstract :
The newly introduced Microprocessor Architecture for Java Computing (MAJC) supports parallelism in a hierarchy of levels: multiprocessors on chip, vertical micro threading, instruction level parallelism via a very long instruction word architecture (VLIW) and SIMD. The first implementation, MAJC 5200, includes some key features of MAJC to realize a high performance multimedia processor. Two CPUs running at 500 MHz are integrated into the chip to provide 6.16 GFLOPS and 12.33 GOPS with high speed interfaces providing a peak input-output (I/O) data rate of more than 4.8 GBytes/second. The chip is suitable for a number of applications including graphics/multimedia processing for high-end set-top boxes, digital voice processing for telecommunications, and advanced imaging
Keywords :
Java; digital signal processing chips; image processing; instruction sets; multimedia computing; multiprocessing systems; parallel architectures; video signal processing; 12.33 GFLOPS; 4.8 Gbyte/s; 500 MHz; 6.16 GFLOPS; MAJC 5200; Microprocessor Architecture for Java Computing; SIMD; VLIW; advanced imaging; digital voice processing; graphics processing; high speed interfaces; high-end set-top boxes; image processing; instruction level parallelism; multimedia processing; multimedia processor; multiprocessors; telecommunications; vertical micro threading; very long instruction word architecture; video processing; Application software; Central Processing Unit; Communication system control; Computer architecture; Control systems; Hardware; Java; Microprocessors; Parallel processing; VLIW;
Conference_Titel :
Image Processing, 2000. Proceedings. 2000 International Conference on
Conference_Location :
Vancouver, BC
Print_ISBN :
0-7803-6297-7
DOI :
10.1109/ICIP.2000.899310
