New tunnel-FET architecture with enhanced ION and improved Miller Effect for energy efficient switching

Tunneling Field Effect Transistors (TFET) are promising devices to respond to the demanding requirements of future technology nodes. The benefits of the TFETs are linked to their sub-60mV/decade sub-threshold swing, a prerequisite for scaling the supply voltage well below 1V. Main research efforts are currently dedicated to improving the on current (I_ON) level in a TFET. However, from the circuit point of view the device capacitances are equally important. It is known that the drain-to-gate capacitance in a TFET is almost equal to the gate capacitance in moderate and strong inversion regimes. Due to enhanced Miller Effect, they are known to exhibit large over/undershoot in transient operation as compared to CMOS. Therefore, the effort on improving I_ON should be simultaneous to an effort of reducing the Miller capacitance (C_MILLER). This work proposes a new architecture which addresses both these issues.