Hierarchical decomposition system and its availability for network solution

Author

Nishigaki, Masakatsu ; Tanaka, Nobuyuki ; Asai, Hideki

Author_Institution

Dept. of Opt-Electron. & Mech. Eng., Shizuoka Univ., Hamamatsu, Japan

fYear

1991

fDate

11-14 Jun 1991

Firstpage

884

Abstract

For efficient circuit simulation, several network tearing techniques have been studied. The authors describe a hierarchical decomposition system, HIDE, and verify its availability for the network solution by the direct method. This system has a graphic circuit editor, GRACE, a translator, LINKER, into the hierarchical structural description language HAL, and the subsystem HiDe, which performs automatic partition of the circuit into gate level subcircuits hierarchically, utilizing the HAL netlist. The authors discuss the hierarchical tearing algorithm for large scale circuits. The authors apply this system to transistor-transistor-logic (TTL) and MOS circuits and verify its availability for the matrix solution

Keywords

MOS integrated circuits; circuit analysis computing; integrated logic circuits; large scale integration; logic CAD; transistor-transistor logic; GRACE; HAL; HIDE; HiDe; LINKER; LSI; MOS circuits; TTL; automatic partition; circuit partitioning; circuit simulation; gate level subcircuits; graphic circuit editor; hierarchical decomposition system; hierarchical structural description language; hierarchical tearing algorithm; large scale circuits; logic ICs; matrix solution; network tearing techniques; transistor-transistor-logic; translator; Availability; Circuit simulation; Delay; Digital circuits; Graphics; Integrated circuit interconnections; Labeling; Large-scale systems; Matrix decomposition; Mechanical engineering;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1991., IEEE International Sympoisum on

Print_ISBN

0-7803-0050-5

Type

conf

DOI

10.1109/ISCAS.1991.176505

Filename

176505