Title :
Primitive interval labelled net model and timing modelling of logic circuits
Author :
Chiu, Peter P K ; Cheung, Y.S.
Author_Institution :
Dept. of Electron. Eng., Hong Kong Polytech., Kowloon, Hong Kong
Abstract :
A reduced version of the interval labeled net model called the primitive interval labeled net model is introduced. By incorporating a projection operator which is based on applying the if-then clause representation of Boolean functions to multivalued logic circuits, the primitive interval labeled net model is powerful enough to model multivalued logic circuits with timing information and all properties of the interval labeled net. This facilitates a better implementation of the verification and simulation than that using the former net model. The number of token types is reduced from four to two. This model involves simpler types of net adjacency relations. The power of the approach is demonstrated by a logic circuit implemented using logic gates with different rise and fall times
Keywords :
Boolean functions; logic design; many-valued logics; Boolean functions; if-then clause; logic circuits; modelling; multivalued logic circuits; net adjacency relations; net model; primitive interval labeled net model; projection operator; simulation; timing information; verification; Boolean functions; Circuit simulation; Inverters; Logic circuits; Logic design; Logic gates; Microcomputers; Multivalued logic; Power system modeling; Timing;
Conference_Titel :
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN :
0-7803-0050-5
DOI :
10.1109/ISCAS.1991.176517