DocumentCode
2830012
Title
Balanced locality-aware packet schedule algrorithm on multi-core network processor
Author
He, Pengcheng ; Wang, JinLin ; Deng, Haojiang ; Zhang, Wu
Author_Institution
Nat. Network New Media Eng. Res. Center, Chinese Acad. of Sci., Beijing, China
Volume
3
fYear
2010
fDate
21-24 May 2010
Abstract
Previous work has shown that processor affinity is one effective way to improve the performance of SMP systems. A detailed analysis of cache characteristics on network processor is carried out. The result shows that network packet processing can also use cache affinity to gain performance improvements by reduce the miss rate of instruction cache and data cache. A schedule algorithm for multi-core network processor taking both load balancing and packet affinity into account is proposed, called BLA. BLA try to schedule packets from the same flow to the same core while keeping work load balanced between cores. The result shows that, BLA can reduce the number of missed cache access by 13%, while the load difference between cores is controlled within 2%.
Keywords
cache storage; microprocessor chips; processor scheduling; resource allocation; SMP system performance; balanced locality-aware packet schedule algorithm; cache access; cache affinity; cache characteristics; data cache; instruction cache; load balancing; multicore network processor; network packet processing; performance improvement; processor affinity; Acoustical engineering; Acoustics; Delay; Electronic mail; Helium; Jitter; Performance gain; Processor scheduling; Scheduling algorithm; Throughput; Cache Affinity; Locality-aware; Multi-core; Network Processor; Schedule;
fLanguage
English
Publisher
ieee
Conference_Titel
Future Computer and Communication (ICFCC), 2010 2nd International Conference on
Conference_Location
Wuhan
Print_ISBN
978-1-4244-5821-9
Type
conf
DOI
10.1109/ICFCC.2010.5497642
Filename
5497642
Link To Document