DocumentCode
2830348
Title
Metastability requirements for a 2 GHz CMOS ΔΣ modulator
Author
Stubberud, Peter ; Dagher, Elias H.
Author_Institution
Dept. of Electr. & Comput. Eng., UNLV, Las Vegas, NV, USA
fYear
2005
fDate
16-18 Aug. 2005
Firstpage
263
Lastpage
268
Abstract
This paper presents the design of a second order, single bit, CMOS, continuous-time analog to digital delta sigma modulator (ΔΣM) which samples at 2 GHz, consumes 18 mW at 1.8 V and has a 79 dB signal-to-noise ratio (SNR) over a 1.23 MHz bandwidth. Because the comparators metastability limited the ΔΣM´s performance, this paper focuses on the design, analysis, and testing of the ΔΣM´s comparator. The ΔΣM´s measured performance is also presented.
Keywords
CMOS integrated circuits; analogue-digital conversion; circuit stability; comparators (circuits); delta-sigma modulation; 1.23 MHz; 1.8 V; 18 mW; 2 GHz; CMOS ΔΣ modulator; CMOS delta sigma modulator; analog-to-digital delta sigma modulator; comparator metastability; continuous-time delta sigma modulator; metastability requirement; single-bit delta sigma modulator; Bandwidth; Delta-sigma modulation; Digital filters; Dynamic range; Filtering; Frequency; Metastasis; Receivers; Sampling methods; Signal to noise ratio;
fLanguage
English
Publisher
ieee
Conference_Titel
Systems Engineering, 2005. ICSEng 2005. 18th International Conference on
Print_ISBN
0-7695-2359-5
Type
conf
DOI
10.1109/ICSENG.2005.53
Filename
1562862
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