Experiments using CMOS neural network chips as pattern/character recognizers

Two prototype chips of an all-MOS implementation of a new architecture have been designed and then fabricated and tested. Real-time experiments on the prototype chips were conducted to demonstrate the use of the new neural circuit as a pattern/character recognizer. Both software dynamic learning schemes and on-chip digital hardware learning circuitry have successfully stored the desired patterns in the network. The execution time of the real-time experiments was in the microseconds range with low power dissipation in the 1-mW range. Dedicated interface circuitries and software environments have been built to successfully demonstrate the use of the prototype chip as a pattern recognizer/classifier