Neural-based analog trainable vector quantizer and digital systolic processors

Architectures and detailed circuit designs of one analog trainable neural chip and one-digital systolic-processor chip are presented. The analog vector quantizer chip performs full search in a massively parallel fashion with an expandable winner-take-all circuitry which can achieve a 10-b resolution. A high compression ratio of 33 is feasible in many image compression applications. Extensive design of a digital systolic-processor chip has been conducted. Circuit blocks, data communication, and microcodes are created to support either the ring-connected or the mesh-connected systolic array for the retrieving and learning phases of the neural network operation. The digital neural chip can also be configured to implement fuzzy logic systems