Efficient calibration of binary-weighted networks using a mixed analogue-digital RAM

Author

Leme, C.A. ; Franca, J.E.

Author_Institution

Dept. of Electr. & Comput. Eng., Inst. Superior Tecnico, Lisboa, Portugal

fYear

1991

fDate

11-14 Jun 1991

Firstpage

1545

Abstract

The architecture and design methodology are described for an area-efficient calibration network organized as a mixed analog-digital RAM (random-access memory) which can be easily controlled and which possesses a very compact layout. The density of the calibrating RAM, expressed in terms of the number of calibrating arrays and of calibrating elements in each array, depends not only on the resolution and element matching accuracy of the network to be calibrated, but also on the calibrating elements themselves. Such a calibration network can be used in any data conversion system based on networks of binary-weighted elements. A CMOS IC implementation is described

Keywords

CMOS integrated circuits; calibration; data conversion; digital integrated circuits; random-access storage; ADC; CMOS IC; DAC; architecture; binary-weighted networks; calibration network; compact layout; data conversion system; design methodology; element matching accuracy; mixed analogue-digital RAM; random-access memory; Analog-digital conversion; Calibration; Capacitors; Computer architecture; Data conversion; Design methodology; Fabrication; Random access memory; Read-write memory; Resistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1991., IEEE International Sympoisum on

Print_ISBN

0-7803-0050-5

Type

conf

DOI

10.1109/ISCAS.1991.176671

Filename

176671