Title :
Space-efficient implementation of binary-tree architectures in arrays containing faulty processing elements
Author_Institution :
Dept. of Appl. Math. & Inf., Ryukoku Univ., Siga, Japan
Abstract :
Presents a new approach for implementing a binary tree architecture (BTA) in a rectangular array of processing elements (PEs), some of which are faulty. The given array is bisected in such a way that the numbers of good PEs contained in the subarrays after the bisection are within the difference of one. Such a bisection is repeated until subarrays of a certain size are obtained. The subarrays reached are neither rectangular nor of the same shape or size. The problem of assigning the nodes of the desired BTA to good PEs in such subarrays and the problem of routing data paths to construct a tree architecture are solved
Keywords :
VLSI; circuit layout CAD; microprocessor chips; parallel architectures; trees (mathematics); binary-tree architectures; bisection; data path routing; faulty processing elements; multiprocessor arrays; partitioning; rectangular array; space efficient implementation; Binary trees; Circuit faults; Data processing; Fault tolerance; Informatics; Integrated circuit manufacture; Mathematics; Routing; Shape; Tiles;
Conference_Titel :
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN :
0-7803-0050-5
DOI :
10.1109/ISCAS.1991.176687
