Neural networks for digital adder

A description is presented of a binary adder using the Hopfield type neural network in which false operations due to local minimum equilibria are avoided. Emphasis is placed on the procedure to correct the false operations by introducing stable conditions of a neuron cell. In addition to this binary adder, the Hopfield type adder with a carry-look-ahead circuit is described. Furthermore, the construction of the proposed adder using CMOS inverters is described. The simulation results show that the proposed adder can achieve high performance operation because of an almost constant operation time, regardless of increase in the number of bits in the circuit