A VLSI architecture for gray-scale morphological filtering and its application

The authors propose a new VLSI architecture for morphological filtering. It reduces the need of arithmetic addition and subtraction by a simple logical candidate selection. Hardware complexity is simplified with pipeline operations. The word-parallel bit-pipeline architecture is suitable for high-speed processing while the bit-serial architecture is suitable for large structuring element. A bit-level systolic design is also demonstrated. This architecture can be applied to distance transformation. Fast real-time implementation is feasible through these concise architectures