Transistor-level CMOS gate models for timing analysis and simulation

Author

Rumin, N.C. ; Dagenais, M. ; Zhang, W.

Author_Institution

Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada

fYear

1991

fDate

11-14 Jun 1991

Firstpage

2156

Abstract

The authors developed a transistor-level CMOS gate model which predicts output transition and delay times with an accuracy which is usually within 10% of SPICE. The model uses constant grounded capacitors to account for storage effects, which makes it applicable in timing analysis and simulation programs which use point-relaxation solution techniques. The authors present the model for a CMOS inverter, which then serves as the basis for modeling CMOS NAND and NOR gates, where the intermediate node capacitances have to be considered

Keywords

CMOS integrated circuits; delays; insulated gate field effect transistors; logic gates; semiconductor device models; CMOS NAND gates; CMOS NOR gates; CMOS inverter; MOSFET capacitance model; constant grounded capacitors; delay times; intermediate node capacitances; output transition time; point-relaxation solution techniques; simulation; timing analysis; transistor-level CMOS gate model; Analytical models; CMOS logic circuits; Circuit simulation; Circuit testing; Delay; MOSFET circuits; Parasitic capacitance; SPICE; Semiconductor device modeling; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1991., IEEE International Sympoisum on

Print_ISBN

0-7803-0050-5

Type

conf

DOI

10.1109/ISCAS.1991.176713

Filename

176713