DocumentCode
2832725
Title
Stray-insensitive sample-delay-hold buffers for high-frequency switched-capacitor filters
Author
Rijns, J.J.F. ; Wallinga, H.
Author_Institution
MESA Inst., Twente Univ., Enschede, Netherlands
fYear
1991
fDate
11-14 Jun 1991
Firstpage
1665
Abstract
Two high-frequency switched-capacitor sample-delay-hold (SDH) buffers are presented. The circuits provide a correct transition from the continuous-time to the discrete-time domain or vice versa. Experimental results show an excellent frequency behavior for clock frequencies up to 25 MHz
Keywords
buffer circuits; frequency response; sample and hold circuits; switched capacitor filters; video equipment; 25 MHz; clock frequencies; continuous time to discrete time domain transition; frequency response; high-frequency switched-capacitor filters; sample-delay-hold buffers; stray insensitivity; video frequency filters; Clocks; Delay; Discrete transforms; Equations; Filters; Frequency; Signal processing; Switching circuits; Synchronous digital hierarchy; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN
0-7803-0050-5
Type
conf
DOI
10.1109/ISCAS.1991.176716
Filename
176716
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