Analysis and modeling of MOS devices with gate oxide short failures

Author

Segura, J. ; Rubio, A. ; Figueras, J.

Author_Institution

Dept. de Fisica, Univ. de les Illes Balears, Spain

fYear

1991

fDate

11-14 Jun 1991

Firstpage

2164

Abstract

A circuit level model for failures causing shorts in the oxide of the gate electrode (GOS) is presented. Experimental results show that the influence of the width of a short between gate and channel in a MOS device is low in comparison with the location in the length direction. The model takes advantage of this result. A unidimensional (length) model for GOS faults is proposed. The experimental results have been obtained by measuring devices with faults where the failures have been introduced by design. The model reduces the complexity of electrical simulations (in comparison with previous unidimensional models) when parametric deviations on an assumed GOS-faulty circuit are analyzed. Results verifying the adequacy of the models and comparison with other research data are presented, considering the effect of the failure on the input and output characteristics of the devices

Keywords

failure analysis; insulated gate field effect transistors; semiconductor device models; semiconductor device testing; short-circuit currents; GOS faults; MOS devices; MOS transistors; circuit level model; electrical simulations; gate oxide short failures; input characteristics; output characteristics; unidimensional model; Analytical models; Circuit faults; Circuit testing; Computational modeling; Electrodes; Failure analysis; Logic; MOS devices; MOSFETs; Surveillance;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1991., IEEE International Sympoisum on

Print_ISBN

0-7803-0050-5

Type

conf

DOI

10.1109/ISCAS.1991.176718

Filename

176718