A physical timing model for digital bipolar ECL circuits

The authors present an accurate physical timing model for large bipolar emitter-coupled-logic (ECL) circuits. A delay model is derived based on device equations and average branch current analysis, and no exhaustive preprocessing or table interpolation is required. The dynamic fanout effects of the ECL circuits can be incorporated by an accurate fanout modeling approach combined with an effective fanout collapsing technique. In addition, the use of a parametric correction scheme permits greater freedom in handling complex delay-sensitive effects such as high-level injection and bipolar parasitic resistances than would otherwise be possible. This delay model with input waveform effects provides delay estimates that are typically within 10% of SPICE estimates