Size optimization for CMOS basic cells of VLSI

The authors describe an approach for solving the transistor size optimization problem with a time delay constraint for a basic VLSI CMOS cell. A set of optimal transistor sizes that provide a delay with circuit analysis accuracy can be obtained with the approximate surface generated from a limited number of circuit evaluations for the basic cell. During one of the iterations of the optimization process, the optimal point obtained from the approximate surface will be used as the new nominal point for the next iteration. The region on the approximate surface converges to a section of the real optimum surface with circuit analysis accuracy as the final nominal point converges to the optimal