Title :
Effect of VLSI interconnect layout on electromigration performance
Author :
Atakov, E.M. ; Sriram, T.S. ; Dunnell, D. ; Pizzanello, S.
Author_Institution :
Digital Equipment Corp., Hudson, MA, USA
fDate :
March 31 1998-April 2 1998
Abstract :
We characterized the reliability of multiple-via contacts, as well as the impact of the contact current direction on the failure statistics and short-length effects in Ti-Al(Cu)-Ti-TiN lines. A significant difference between the sheet resistances of the top and bottom shunting layers results in a bimodal failure time distribution for the downward electron flow direction. It also causes a significant difference in the short-length resistance saturation for the two current directions.
Keywords :
VLSI; aluminium alloys; copper alloys; electrical contacts; electromigration; failure analysis; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; integrated circuit testing; titanium; titanium compounds; Ti-Al(Cu)-Ti-TiN lines; Ti-AlCu-Ti-TiN; VLSI interconnect layout; bimodal failure time distribution; bottom shunting layer; contact current direction; current direction; downward electron flow direction; electromigration performance; failure statistics; multiple-via contacts; reliability; sheet resistance; short-length effects; short-length resistance saturation; top shunting layer; Annealing; Current density; Electric resistance; Electromigration; Electrons; Integrated circuit interconnections; Stress; Testing; Tin; Very large scale integration;
Conference_Titel :
Reliability Physics Symposium Proceedings, 1998. 36th Annual. 1998 IEEE International
Conference_Location :
Reno, NV, USA
Print_ISBN :
0-7803-4400-6
DOI :
10.1109/RELPHY.1998.670668
