Prototype chip set for systolic wave digital filters employing optimal two phase clocking

A general method for the implementation of one-dimensional word-level systolic arrays using bit-level systolic arrays is developed. The relative merits of single- and two-phase clocking are examined. An analysis indicates an advantage of two-phase clocking for the systems studied in respect to area usage and potential speed. The results are applied to the design of a prototype unit-element cascade wave digital filter whose bit-sliced design is partitioned into a set of chips and fabricated using gate array technology, producing the first bit-level systolic wave digital filter in hardware. Test results verify the design and give the relationship between the systolic cell delay and the system clock rate. The system is capable of simple filtering operations at 2 MHz, independent of the data wordlength