DocumentCode
2832978
Title
Systolic parasitic insensitive switched capacitor and digital filters
Author
Raut, R. ; Bhattcharyya, B.B. ; Faruque, S.M.
Author_Institution
Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
fYear
1991
fDate
11-14 Jun 1991
Firstpage
1689
Abstract
A systematic method for implementing parasitic-insensitive (PI) switched capacitor filters (SCFs) and digital filters (DIGFs) using systolic array architecture (SAA) is introduced. A signal flow graph (SFG) method is used for a general treatment of first and second order filters. Systematic reduction of the SFGs leads to a number of SAA implementations which will require minimal hardware. Practical aspects of implementation are discussed. Simulation results are reported
Keywords
digital filters; graph theory; network analysis; network synthesis; switched capacitor filters; systolic arrays; digital filters; first-order filters; second order filters; signal flow graph; switched capacitor filters; systolic array architecture; Circuit simulation; Circuits and systems; Computer architecture; Costs; Digital filters; Flow graphs; Hardware; Switched capacitor circuits; Switching circuits; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN
0-7803-0050-5
Type
conf
DOI
10.1109/ISCAS.1991.176732
Filename
176732
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