Title :
SMAS: a program for the concurrent state reduction and state assignment of finite state machines
Author :
Avedillo, M.J. ; Quintana, J.M. ; Huertas, J.L.
Author_Institution :
Centro Nacional de Microelectron., Sevilla, Spain
Abstract :
A state assignment algorithm for PLA-based machines which produces as assignment of nonnecessarily distinct and eventually incompletely specified codes is presented. In this approach, state reduction and state assignment are concurrently dealt with, and a restricted state splitting technique is explored. The algorithm is particularly appropriate for machines with compatibility relations among states because the potentials of state merging are exploited during the state assignment step. The input to SMAS, the program implementing the algorithm, is a symbolic cover of the FSM. The output is a Boolean representation of both next state and output functions suitable to be minimized with ESPRESSO. The machines in the MCNC benchmark set are used to test the algorithm and to compare it with a well-known state assignment program
Keywords :
logic CAD; logic arrays; state assignment; Boolean representation; CAD; ESPRESSO; FSM; MCNC benchmark set; PLA-based machines; SMAS; concurrent state reduction; finite state machines; programmable logic array; state assignment; state merging; state splitting technique; Algorithm design and analysis; Analog circuits; Automata; Benchmark testing; Encoding; Logic testing; Merging; Minimization methods; Sequential analysis; System testing;
Conference_Titel :
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN :
0-7803-0050-5
DOI :
10.1109/ISCAS.1991.176749
