Framework for architecture synthesis of data conversion systems employing binary-weighted capacitor arrays

A framework for the architecture synthesis of analog-to-digital (A/D) and digital-to-analog (D/A) conversion systems using binary-weighted C arrays is described. The ability to handle both single and segmented arrays as well as to include calibration networks makes it possible to cover a wide range of specifications. The netlist of the synthesized architecture, including the specifications internally determined for the circuit components, can be interfaced through a dedicated interface management routine with a variety of lower level design environments to achieve a great design flexibility