TiGeR, the Transmeta Instruction GEneratoR: A Production Based, Pseudo Random Instruction x86 Test Generator

Real world software applications, in addition to carefully crafted test cases, are often used in microprocessor and system verification as they exercise the interaction of many different functional blocks in the processor In the case of dynamic binary translation based microprocessors like Efficeon and Crusoe, they also exercise the code morphing software (CMS), the firmware layer that provides x86 compatibility. However this approach has limitations in that it is exceedingly difficult to identify, isolate, reproduce and debug failures and no single application may exercise most of the architectural corner cases of the CPU. Hence we have developed an x86 random instruction generator that generates code that has the characteristics of typical 32 bit protected mode programs. The instruction generator is highly configurable and deterministic, and has been successfully used in the verification of the Efficeon line of processors through all its phases of development and productization. The instruction generator is production based, in the sense that it generates code based on a set of rules called productions