DocumentCode
2833626
Title
Maximizing the fault coverage in complex circuits by minimal number of signatures
Author
Wunderlich, Hans-Joachim ; Ströle, Albrecht P.
Author_Institution
Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
fYear
1991
fDate
11-14 Jun 1991
Firstpage
1881
Abstract
Methods to minimize the number of evaluated signatures without reducing the fault coverage are presented. This is possible because the signatures can influence one another during the test execution. For a fixed test schedule a minimal subset of signatures can be selected, and for a predetermined minimal subset of signatures the test schedule can be constructed such that the fault coverage is maximum. Both approaches result in significant hardware savings when a self-test is implemented
Keywords
built-in self test; computerised signal processing; logic testing; BIST; complex circuits; fault coverage maximisation; hardware savings; response compaction; signature analysis; signature number minimization; test scheduling; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Fault tolerance; Hardware; Logic testing; Pattern analysis; Registers; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN
0-7803-0050-5
Type
conf
DOI
10.1109/ISCAS.1991.176774
Filename
176774
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