DocumentCode
2833639
Title
A Pipelined Memory-efficient Architecture for Ultra-long Variable-size FFT Processors
Author
He, Chen ; Qiang, Wu ; Zhenbin, Gao ; Hongxing, Wan
Author_Institution
Electr. Eng. Dept., Beijing Inst. of Technol., Beijing
fYear
2008
fDate
Aug. 29 2008-Sept. 2 2008
Firstpage
357
Lastpage
361
Abstract
A scheme of ultra-long variable-size pipelined FFT processor is presented and a prototype is implemented with one FPGA, which may compute various 4n (n = 1 ~ 10) points FFT at a speed as high as 150 MHz. The solutions are to transform the one-dimension FFT to two-dimension repeatedly, and propose an efficient twiddle-factor memory compression method. Based on two techniques storage resource of FFT processor can be reduced largely.
Keywords
fast Fourier transforms; field programmable gate arrays; memory architecture; microprocessor chips; pipeline processing; FPGA; pipelined memory-efficient architecture; twiddle-factor memory compression; ultra-long variable-size FFT processor; Application specific integrated circuits; Computer architecture; Computer science; Concurrent computing; Digital signal processing; Discrete Fourier transforms; Field programmable gate arrays; Memory architecture; Pipeline processing; Signal processing algorithms;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Science and Information Technology, 2008. ICCSIT '08. International Conference on
Conference_Location
Singapore
Print_ISBN
978-0-7695-3308-7
Type
conf
DOI
10.1109/ICCSIT.2008.160
Filename
4624891
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