Parallel logic simulation on a workstation cluster

Author

Murakami, Tetsuya ; Wada, Koichi ; Okano, Shin-ichi

Author_Institution

Tsukuba Univ., Ibaraki, Japan

fYear

1995

fDate

17-19 May 1995

Firstpage

268

Lastpage

271

Abstract

A high speed logic simulator is a requisite tool in designing VLSIs. This paper presents a high performance parallel logic simulator on a workstation cluster. The conservative method is used for an algorithm of parallel logic simulator. The null message and the query computation algorithm are used to solve deadlocks. This paper proposes an event clumping that can reduce the number of messages effectively. The simulation has been performed on the workstation cluster for evaluation. The results of evaluation showed that the proposed method exhibited the speed of 42 times faster than the conventional null message algorithm. In the case of the query computation algorithm, the gain of the event clumping was 4.2 on five processors

Keywords

VLSI; circuit analysis computing; discrete event simulation; engineering workstations; integrated circuit design; logic CAD; logic partitioning; parallel algorithms; VLSI design; conservative method; deadlocks; discrete event simulation; event clumping; message algorithm; parallel algorithm; parallel logic simulation; performance parallel logic simulator; query computation algorithm; workstation cluster; Circuit simulation; Clustering algorithms; Computational modeling; Discrete event simulation; Hardware; Large scale integration; Logic circuits; Logic design; System recovery; Workstations;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Computers, and Signal Processing, 1995. Proceedings., IEEE Pacific Rim Conference on

Conference_Location

Victoria, BC

Print_ISBN

0-7803-2553-2

Type

conf

DOI

10.1109/PACRIM.1995.519459

Filename

519459