DocumentCode
2833656
Title
Relating aliasing in signature analysis to test length and register design
Author
Franco, Piero ; Saxena, Nirmal ; McCluskey, Edward J.
Author_Institution
Comput. Syst. Lab., Stanford Univ., CA, USA
fYear
1991
fDate
11-14 Jun 1991
Firstpage
1889
Abstract
Recently derived upper bounds on the aliasing probability for serial signature analysis using the Bernoulli error model are reviewed. Since the bit error probability p is unrestricted in general, upper bounds independent of p are emphasized. It is also shown that even for exhaustive testing, the aliasing probability for non-primitive polynomials with short periods does not reach its asymptotic value of all p
Keywords
logic testing; signal processing; Bernoulli error model; aliasing probability; bit error probability; exhaustive testing; register design; response compaction; signature analysis; test length; upper bounds; Error probability; Polynomials; Testing; Upper bound;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN
0-7803-0050-5
Type
conf
DOI
10.1109/ISCAS.1991.176776
Filename
176776
Link To Document