An advanced programmable 2D-convolution chip for, real time image processing

Author

Hecht, V. ; Ronner, K.

Author_Institution

Lab, fuer Informationstechnologie, Hannover Univ.

fYear

1991

fDate

11-14 Jun 1991

Firstpage

1897

Abstract

An advanced defect-tolerant systolic array implementation of the 2-D convolution algorithm for real-time image processing applications is presented. The chip differs from available convolution chips in the maximum kernel size of 256 taps, the ability to convolve one video signal with up to four independent coefficient masks, support of adaptive filtering, on-chip delay lines, and implemented special processing of frame borders. Defect tolerance, e.g., reconfiguration techniques, are implemented in order to enhance yield and reliability, especially for future large area implementations

Keywords

circuit reliability; computerised picture processing; digital signal processing chips; fault tolerant computing; real-time systems; systolic arrays; adaptive filtering; defect-tolerant; frame borders; independent coefficient masks; large area implementations; on-chip delay lines; programmable 2D-convolution chip for, real time image processing; reconfiguration techniques; reliability; systolic array; yield enhancement; Adaptive filters; Biomedical imaging; Convolution; Convolvers; Delay lines; Hardware; Image edge detection; Image processing; Kernel; Pattern recognition;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1991., IEEE International Sympoisum on

Print_ISBN

0-7803-0050-5

Type

conf

DOI

10.1109/ISCAS.1991.176778

Filename

176778