Robust Vera coding techniques for gate-level and tester-compliant SoC verification environments

Real world requirements such as low-power modes of operation and multiple clock domains often necessitate gate-level system-on-chip (SoC) verification environments. Additional complexities introduced by tester compliance impose restrictions on the control and repeatability of simulations over all situations, including register-transfer-level (RTL) and different gate-level conditions. Making full use of the Vera high-level verification language in these circumstances requires special considerations and techniques not normally applied in a module-level RTL testbench. If the intent is to reuse Vera monitors, drivers and result-checkers in the gate-level SoC environment then the code must be designed appropriately. This paper first explores the generic issues of interacting with a gate-level SoC in a tester compliant manner and then proceeds to derive Vera coding guidelines that ensure robust operation across a range of testbench abstractions from module-level RTL through to tester-compliant gate-level SoC implementations.