Functional verification of pipelined processors: a case study

Author

Mishra, Prabhat ; Dutt, Nikil ; Kashai, Yaron

Author_Institution

Dept. of Comput. & Info. Sci. & Eng., Florida Univ., USA

fYear

2004

fDate

9-10 Sept. 2004

Firstpage

79

Lastpage

84

Abstract

Functional verification of pipelined processors is one of the major bottlenecks in current system-on-chip (SOC) design methodology. A significant bottleneck in the validation of such systems is the lack of a suitable functional coverage metric. This paper presents a test generation and functional coverage estimation framework for pipelined processors using Specman Elite. We have applied this methodology on a VLIW DLX architecture to demonstrate the usefulness of our approach.

Keywords

formal verification; hardware description languages; integrated circuit design; parallel architectures; pipeline processing; system-on-chip; Specman Elite; VLIW DLX architecture; functional coverage estimation; functional coverage metric; functional verification; pipelined processors; system-on-chip design; test generation; Automatic testing; Computer aided software engineering; Design methodology; Embedded computing; Hardware design languages; Hazards; Instruction sets; Microprocessors; Pipelines; Power generation;

fLanguage

English

Publisher

ieee

Conference_Titel

Microprocessor Test and Verification (MTV'04), Fifth International Workshop on

ISSN

1550-4093

Print_ISBN

0-7695-2320-X

Type

conf

DOI

10.1109/MTV.2004.14

Filename

1563076