KISS-16V1: a 16 bit signal processor

Author

Schuck, J. ; Ebert, H. ; Mahlich, G. ; Preissner, J. ; Sahm, H. ; Weinsziehr, D. ; Hellwig, K. ; Bauer, H. ; Lorenz, D.

Author_Institution

Philips Kommunikations Ind. AG, Nuernberg, Germany

fYear

1991

fDate

11-14 Jun 1991

Firstpage

1905

Abstract

The authors describe the architecture and design of the 1 6-b low-power CMOS fixed-point signal processor KISS-16V1. The 16-b data and instructions are processed in one 50-ns cycle. The KISS-16V1 is a digital-signal processor (DSP) with a multibus Harvard architecture. Its new architectural features and its sophisticated instruction set are optimized for digital telecommunications, especially for GSM. A power-down mode together with the capability of memory and multiplier standby operation make this DSP well suited for hand-held devices. A design strategy based on the extensive use of cell compilers and synthesis tools reduces the design period of further DSP derivations to a minimum. This flexible concept allows adaptation of the device for enhanced requirements of GSM as well as for other signal processing applications. This DSP is a significant step toward an all-digital-on-one-chip solution for the GSM full-rate channel

Keywords

CMOS integrated circuits; computerised signal processing; digital signal processing chips; telecommunications computing; 16 bit; 50 ns; DSP; GSM full-rate channel; KISS-16V1; cell compilers; design strategy; digital telecommunications; digital-signal processor; fixed-point signal processor; hand-held devices; instruction set; low-power CMOS; multibus Harvard architecture; multiplier standby operation; power-down mode; synthesis tools; Baseband; Cryptography; Digital signal processing; GSM; Hardware; Land mobile radio; Registers; Signal processing; Signal processing algorithms; Speech;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1991., IEEE International Sympoisum on

Print_ISBN

0-7803-0050-5

Type

conf

DOI

10.1109/ISCAS.1991.176780

Filename

176780