DocumentCode
2833759
Title
Design of overturned-stairs tree multipliers
Author
Mou, Zhi-Jian ; Schwarz, Albrechet ; Jutand, Francis
Author_Institution
Dept. of Electron., Telecom Paris Univ., France
fYear
1991
fDate
11-14 Jun 1991
Firstpage
1916
Abstract
The design of overturned stairs (OS) tree multipliers for 2´s complement numbers is presented. A 2´s complement multiplication algorithm other than the Baugh-Wooley method is used. A 16×16 multiplier design is studied in detail. The generation of arbitrary N×N multipliers is addressed. It is shown that OS tree multipliers can be systematically designed. A regular and compact layout can be obtained. Tree-type design leads to high-speed computation but increases the chip area requirement. The authors give a comparison between their design and a conventional one
Keywords
digital arithmetic; integrated logic circuits; logic design; multiplying circuits; trees (mathematics); 2´s complement numbers; chip area; compact layout; high-speed computation; multiplication algorithm; overturned-stairs tree multipliers; Telecommunications;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN
0-7803-0050-5
Type
conf
DOI
10.1109/ISCAS.1991.176783
Filename
176783
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