Hot electron degradation and unclamped inductive switching in submicron 60-V lateral DMOS

Hot electron degradation of 60-V lateral N-LDMOS devices integrated in a 0.8-/spl mu/m Bi-CMOS-DMOS twin-well VLSI CMOS process in conjunction with unclamped inductive switching (UIS) is presented for the first time. Two new figures of merit are introduced for reliable L-DMOS designs under both avalanche and saturation conditions. A built-in trade-off is shown to exist between HE degradation and UIS for submicron N-LDMOS devices. Two different techniques, namely, addition of a p-buried layer and P vs. As-doped drain N-LDMOS are investigated through device simulations and experiments to improve HE and UIS performance. Measurements indicate 8/spl times/ enhancement in UIS current for N-LDMOS with a p-buried layer. Although the P-graded drain N-LDMOS offers 2/spl times/ higher UIS current over the As-doped drain device, the measured device parameters deteriorate quickly, maintaining an asymptotic behavior above 10,000 s. Experiments indicate an order of magnitude increase in substrate currents for P-graded drain N-LDMOS when compared to As-doped devices. Simulations corroborate device degradation of P-graded drain N-LDMOS to higher impact ionization in the area of the LOCOS region.