• DocumentCode
    2833848
  • Title

    Mismatch sensitivity of a simultaneously latched CMOS sense amplifier

  • Author

    Sarpeshkar, Rahul ; Wyatt, John L., Jr. ; Lu, Nicky C. ; Gerber, Porter D.

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
  • fYear
    1991
  • fDate
    11-14 Jun 1991
  • Firstpage
    2224
  • Abstract
    The authors introduce a new formula for the sensitivity of a vertically matched CMOS sense amplifier, of the type used in dynamic RAMs (DRAMs) to threshold voltage mismatch, parasitic capacitance mismatch, transconductance mismatch, and bitline load capacitance mismatch. The perturbation approach is rigorous; it avoids most approximations and ad hoc assumptions, and it introduces no free constants to be determined from simulations. The perturbation approach yields an explicit closed-form solution. The formula agrees well with simulations. It is inherently slightly conservative and thus appropriate for use in design
  • Keywords
    CMOS integrated circuits; DRAM chips; amplifiers; network analysis; sensitivity analysis; DRAM sense amplifier; DRAMs; bitline load capacitance mismatch; dynamic RAMs; explicit closed-form solution; formula; mismatch sensitivity; parasitic capacitance mismatch; perturbation approach; simultaneously latched CMOS sense amplifier; threshold voltage mismatch; transconductance mismatch; vertically matched; CMOS technology; Circuits; Closed-form solution; Differential amplifiers; FETs; MOS devices; Parasitic capacitance; Signal design; Threshold voltage; Transconductance;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1991., IEEE International Sympoisum on
  • Print_ISBN
    0-7803-0050-5
  • Type

    conf

  • DOI
    10.1109/ISCAS.1991.176788
  • Filename
    176788