DocumentCode :
2833920
Title :
Automatic test point insertion for pseudo-random testing
Author :
Savaria, Y. ; Youssef, M. ; Kaminska, B. ; Koudil, M.
Author_Institution :
Dept. of Electr. Eng., Ecole Polytech. de Montreal, Que., Canada
fYear :
1991
fDate :
11-14 Jun 1991
Firstpage :
1960
Abstract :
A combination of techniques for efficiently inserting test points is proposed. These techniques refer to three complementary abstraction levels: algorithms, circuits, and layout. The authors deal with pseudo-random testing and present a method of condensing test points based on the notion of fault sector. Based on a set of proposed heuristics, a tool for automatically inserting test points was developed. Experimental results obtained with the tool are presented to indicate that excellent pseudo-random testability can be achieved with few test points. This technique leads to the lowest reported number of test points while significantly reducing the number of random patterns which are required to achieve very close to 100% fault coverage
Keywords :
VLSI; automatic testing; fault location; integrated circuit testing; integrated logic circuits; logic testing; VLSI circuit testing; automatic test point insertion; fault coverage; pseudo-random testing; Automatic control; Automatic test pattern generation; Automatic testing; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Latches; Logic testing; System testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN :
0-7803-0050-5
Type :
conf
DOI :
10.1109/ISCAS.1991.176793
Filename :
176793
Link To Document :
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