Title :
A stochastic model for fault propagation, in combinational circuits
Author :
Sastry, Sarma ; Majumdar, Amitava
Author_Institution :
Dept. of EE-Syst., Univ. of Southern California, Los Angeles, CA, USA
Abstract :
The authors present a new stochastic model for fault propagation in combinational circuits that is sensitive to the structural characteristics of the circuit. Under random testing, fault propagation through a circuit is modeled as a branching process. Due to the presence of fanout, a fault on a gate at level l, once activated, will generate a number of copies of itself, called descendants, at level l+1. Similarly, due to the presence of reconvergent fanout, a fault may cease to propagate. An activated fault is detected if at least one of its descendants is active at the primary outputs. For a fault on a gate at level l, the authors present basic results on the distribution of the number of next-level descendants and the number of kth-level descendants, k⩾l. The importance of these results lies in the fact that they are sensitive to the circuit structure and play a basic role in design for testability
Keywords :
combinatorial circuits; fault location; logic design; logic testing; stochastic processes; branching process; combinational circuits; design for testability; fault propagation; logic circuit testing; random testing; reconvergent fanout; stochastic model; structural characteristics; Circuit faults; Circuit testing; Combinational circuits; Controllability; Design for testability; Electrical fault detection; Event detection; Fault detection; Observability; Stochastic processes;
Conference_Titel :
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN :
0-7803-0050-5
DOI :
10.1109/ISCAS.1991.176794