Title :
Configurable architecture for memory BIST
Author :
Lotfi, Atieh ; Kabiri, Parisa ; Navabi, Zainalabedin
Author_Institution :
CAD Res. Group, Univ. of Tehran, Tehran, Iran
Abstract :
The number of memory components in today´s chips is increasing considerably. Through the limitations on area and number of test pins, it is not feasible to use a separate BIST architecture for testing every memory on the chip. Therefore, it is essential to have a configurable BIST architecture. In this paper, a configurable memory BIST architecture that can test different memories having different sizes and configurations with an arbitrary test algorithm is proposed.
Keywords :
built-in self test; digital storage; logic testing; configurable BIST architecture; configurable memory BIST architecture; memory BIST; test algorithm; Built-in self-test; Generators; Memory architecture; Microprocessors; Random access memory; Writing;
Conference_Titel :
Design & Test Symposium (EWDTS), 2011 9th East-West
Conference_Location :
Sevastopol
Print_ISBN :
978-1-4577-1957-8
DOI :
10.1109/EWDTS.2011.6116571
