Graph partitioning using a reduced connectivity matrix for VLSI applications

The authors present a new algorithm for partitioning VLSI circuits. The algorithm is based on the formulation of a reduced connectivity matrix. The partitioning is performed on this matrix using the concept of cut index. The algorithm heuristically minimizes the number of branches cut between partitions with user control over the size of and the number of partitions. The time complexity of the algorithm has been analytically and experimentally shown to be of order O(n²). The algorithm was implemented using the C programming language and the X-windows environment, and has graphical and netlist input/output interfaces