Title :
An efficient multi-level placement technique using hierarchical partitioning
Author :
Hamada, Takeo ; Cheng, Chung-Kuan ; Chau, Paul M.
Author_Institution :
California Univ., La Jolla, CA, USA
Abstract :
The authors apply ratio cut hierarchical partitioning, which enables efficient multilevel simulated annealing. An overlapping moving window scheme is used to compensate for the effect of partitioning on the placement quality. Due to the hierarchical partitioning, the asymptotic run-time complexity of this algorithm is linear to the circuit size. The system is called PRC (placement by ratio cut partitioning). Experimental results have been consistently better than TimberWolfSC ver.5.6 for the available test cases and show significant run-time reduction for the large test cases of more than 2000 cells. For a 100 K sea of gates test case, a 7% improvement in wirelength over TimberWolfSC ver.5.6 and a more than 50% of savings in CPU time were observed
Keywords :
VLSI; circuit layout CAD; logic arrays; simulated annealing; CPU time savings; PRC; asymptotic run-time complexity; hierarchical partitioning; large test cases; multilevel placement techniques; multilevel simulated annealing; overlapping moving window scheme; placement by ratio cut partitioning; placement quality compensation; run-time reduction; sea of gates; wirelength reduction; Central Processing Unit; Circuit simulation; Circuit testing; Clustering algorithms; Computational modeling; Partial response channels; Partitioning algorithms; Processor scheduling; Simulated annealing; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN :
0-7803-0050-5
DOI :
10.1109/ISCAS.1991.176805
