Fault modeling and test pattern generation in the design of array processors

Deals with the problem of establishing a model for test pattern generation and hierarchical fault coverage during the earliest phases of the design of processor arrays. A general approach, valid for the two intermediate design steps of processor arrays, consisting of identical combinational cells with identical local interconnections, is presented. The classes of architectures considered are iterative logic arrays, and systolic and semisystolic arrays implementing locally recursive algorithms. Three basic abstraction levels can be identified in the synthesis of array architectures: the data flow graph, the signal flow graph, and the array level. The authors introduce a methodology to map the testability and testing techniques identified for each level to the others