Parallel circuit simulation based on nonlinear relaxation methods

The authors describe a number of techniques to perform parallel circuit simulation on a shared-memory multiprocessor using nonlinear relaxation algorithms. These approaches have been implemented on the Alliant FX/80 multiprocessor, which is a shared-memory machine with 8 processors. Various schemes based on the iterated timing analysis (ITA) algorithm exploiting subcircuit-level parallelism are described, including multiple barrier, single barrier, event-driven and unrolled versions of multiple barrier and single barrier. Simulation results on industrial circuits are used to identify the tradeoffs and limitations of each approach. Results indicate that, while event-driven is generally able to provide good speedups, the unrolled schemes are capable of providing better speedups on particular circuit examples